Driving and Control Techniques for CompactPCI Bus under VxWorks

Table of Contents

📘 Abstract
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This article introduces CompactPCI (cPCI) bus and interface technologies, with a focus on PCI configuration space organization and device control under the VxWorks real-time operating system. It explains how cPCI devices are configured, driven, and managed in VxWorks-based systems. Because real-time systems respond to external events primarily through interrupts, hardware interrupt handling is a critical design concern. Under VxWorks, cPCI interrupt processing involves binding external interrupts to interrupt service routines (ISRs) and configuring the interrupt control registers of the PCI9054 interface chip. Semaphores are used within ISRs to synchronize tasks, ensuring reliable and deterministic real-time data acquisition.

Keywords: CompactPCI bus, PCI configuration space, interrupt control, semaphore synchronization

🧭 Introduction
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With growing demand for high-reliability and high-performance industrial systems, the CompactPCI bus has become a widely adopted embedded backplane architecture. CompactPCI combines high bandwidth, rugged Eurocard mechanical design, and open software support, making it suitable for telecommunications, industrial control, medical systems, automation, and data communication platforms.

VxWorks, developed by Wind River Systems, is a widely used embedded real-time operating system (RTOS). It provides deterministic task scheduling, efficient interrupt handling, real-time resource management, and flexible inter-task communication mechanisms. Due to its reliability and real-time guarantees, VxWorks is extensively used in safety- and mission-critical domains such as aerospace, defense, medical devices, and communications.

In petroleum logging surface systems—vehicle-mounted real-time data acquisition and processing platforms—strict real-time requirements apply. These systems issue control commands to downhole instruments and receive large volumes of measurement data, performing real-time control, quality monitoring, data processing, visualization, and storage. Any loss of interrupt response can cause data corruption or operational failure. To meet these requirements, the system described here adopts a CompactPCI hardware architecture and VxWorks software platform to ensure real-time performance, reliability, and maintainability.

🧩 Bus and Interface Technology
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CompactPCI is an open industrial standard defined by the PCI Industrial Computer Manufacturers Group (PICMG). It is fully compatible with conventional PCI in electrical, logical, and software aspects while offering improved mechanical robustness. CompactPCI boards are installed in card cages using standardized 3U or 6U Eurocard form factors.

CompactPCI integrates three key technologies:

The high-performance PCI local bus
Rugged Eurocard mechanical structures
Reliable high-density pin-and-socket connectors

The PCI local bus is a high-performance 32-bit or 64-bit bus with multiplexed address and data lines. It supports multi-master operation and provides efficient interconnection between CPUs, memory subsystems, and peripheral controllers. Operating frequencies originally defined at 33 MHz have expanded to 66 MHz and beyond. At 33 MHz with a 32-bit bus width, PCI achieves a peak bandwidth of 132 MB/s, sufficient for network adapters, storage controllers, and data acquisition cards.

A key feature of PCI is its configuration space, which enables automatic device discovery and resource allocation. System software reads device parameters from configuration space and assigns address resources dynamically, enabling plug-and-play functionality and allowing multiple identical devices to coexist without conflicts.

In this system, user function boards connect to the PCI bus through the PLX PCI9054 interface chip. The PCI9054 is a 32-bit, 33 MHz PCI controller compliant with PCI 2.2 specifications and supports burst transfers up to 132 MB/s. It can operate as both a PCI master and target and provides interfaces to PCI, EEPROM, and a LOCAL bus.

The LOCAL bus supports multiple operating modes (M, C, and J). In the described data acquisition system, the LOCAL bus operates in C mode (target mode). Configuration data for the PCI9054 is stored in an external serial EEPROM (NM93CS56L). During system startup, the PCI9054 loads configuration parameters—including vendor ID, device ID, address ranges, and base addresses—from EEPROM, enabling automatic resource allocation by the host system.

The PCI9054 supports three primary data transfer modes:

PCI Initiator mode: LOCAL bus master accesses PCI memory or I/O space
PCI Target mode: PCI master accesses LOCAL bus registers or memory
DMA mode: PCI9054 transfers data autonomously between PCI and LOCAL buses

In this design, PCI Target mode is used for register-level control and data access.

⚙️ Device Configuration under VxWorks
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VxWorks abstracts many low-level system services, allowing driver developers to focus on device logic rather than resource management. To implement a cPCI device driver, developers must understand the PCI configuration register space, which consists of 256 bytes divided into a standard header region and a device-specific region.

The header region includes fields such as:

Vendor ID and Device ID
Revision ID
Class code
Header type

Base Address Registers (BARs) define how much memory or I/O space a device requires and allow the system to map device resources into the processor’s address space. Writing all 1s to a BAR and reading it back reveals the size of the required address region.

Device Enumeration Process
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Under VxWorks, cPCI device initialization typically follows these steps:

Locate the device using pciFindDevice(), which identifies the bus number, device number, and function number based on vendor and device IDs.
Access configuration space using APIs such as pciConfigInLong() and pciConfigOutLong() to configure BARs, interrupt lines, and command registers.
Map device memory into the system address space and initialize control registers.
Install interrupt handlers and prepare runtime data structures.

An example device initialization routine is shown below:

STATUS Init_IP() {
    if (pciFindDevice(VID_IPCARRIER, DID_IPCARRIER, index,
        &pBusNo, &pDeviceNo, &pFuncNo) != OK) {
        return ERROR;
    }

    pciConfigInLong(pBusNo, pDeviceNo, pFuncNo, 0x10, &BaseAdd0_IPCarrier);
    pciConfigInLong(pBusNo, pDeviceNo, pFuncNo, 0x18, &BaseAdd2_IPCarrier);

    sysMmioMapAdd(
        (BaseAdd2_IPCarrier & PCI_DEV_MMU_MSK),
        PCI_DEV_ADRS_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE,
        VM_STATE_VALID | VM_STATE_WRITABLE
    );

    return OK;
}

🔔 Interrupt Response and Control
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Interrupt handling is central to real-time system performance. In VxWorks, interrupt service routines execute outside all task contexts, eliminating task-switching overhead and ensuring minimal response latency.

The PCI9054 provides an interrupt control/status register at offset 0x68. This register must be configured correctly to enable cPCI interrupts.

Under VxWorks, interrupt configuration involves two key steps:

Connecting the interrupt vector using pciIntConnect()
Enabling interrupts in the PCI9054 control register

STATUS Init_IP_Int() {
    if (pciIntConnect(INUM_TO_IVEC(0x27), IPIsr, 0) == ERROR) {
        return ERROR;
    }

    *(int *)(BaseAdd0_IPCarrier + 0x68) = 0x0f010900;
    return OK;
}

To disable interrupts, the control register is written with 0x0f000000.

Semaphore-Based Synchronization
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To keep ISRs short and efficient, the interrupt routine simply releases a semaphore associated with the event:

void IPIsr() {
    semGive(sem_DepthInt);
}

Binary semaphores in VxWorks provide fast and deterministic synchronization between ISRs and tasks. When a task calls semTake(), it either proceeds immediately or blocks until the ISR signals completion. This mechanism ensures reliable real-time data acquisition without excessive interrupt processing overhead.

✅ Conclusion
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By combining CompactPCI hardware with VxWorks real-time software, the system successfully implements stable and deterministic control of multiple cPCI boards, including DSP processing modules, high-speed and low-speed ADC channels, counters, and depth control units. Practical operation demonstrates that the described CompactPCI driving and interrupt control techniques are feasible and effective. The approach satisfies stringent real-time and reliability requirements, making it well suited for industrial and data acquisition systems based on VxWorks.