Synergy PowerPC VxWorks Example Project: Dual-Processor Template

Table of Contents

Synergy PowerPC Dual-Processor Example Project for VxWorks

This project demonstrates a dual-processor setup (X primary, Y secondary) with:

Multi-processor boot
Shared memory communication
Timers and tick interrupts
VMEbus master/slave access
Serial console interaction
ECC memory checks

It is ready to drop into Tornado IDE with Synergy BSP 1.2+.

1. Project Directory Structure
#


project_root/
├─ config.h
├─ main.c
├─ bootrom/
│  └─ bootrom.hex
├─ Makefile
└─ docs/

config.h: BSP kernel configuration
main.c: Application entry point for X and Y CPUs
bootrom/: Boot ROM images
Makefile: Tornado IDE compatible build script

2. Example `config.h`
#

#ifndef CONFIG_H
#define CONFIG_H

#include "vxWorks.h"
#include "configAll.h"

/* -----------------------------
   Processor & Board Settings
   ----------------------------- */
#define NUM_TTY 2           /* X uses TTY1, Y uses TTY2 */
#define X_CPU 0
#define Y_CPU 1

/* Shared Memory Base/Size for Inter-CPU Communication */
#define SHARED_MEM_BASE 0x4100
#define SHARED_MEM_SIZE 0x1000

/* Include Core BSP Components */
#define INCLUDE_VX_SMP
#define INCLUDE_END
#define INCLUDE_TIMESTAMP
#define INCLUDE_RAM_PAR_ECC
#define ECC_MULTIBIT_MCP_ENABLE TRUE
#define ECC_1BIT_MCP_ENABLE TRUE
#define ECC_TRIGGER_VALUE 32

/* VME Bus Master/Slave Ports */
#define VME_A32_SLV_BUS 0x20000000
#define VME_A32_SLV_SIZE 0x02000000

/* PCI Bus Configuration */
#define PCI_M_SIZE  0x04000000
#define PCI_IO_SIZE 0x00010000
#define INCLUDE_PEX3

/* Flash & File System */
#define INCLUDE_FFS_DRV
#define INCLUDE_DOSFS
#define INCLUDE_FLASH_FILE

#endif /* CONFIG_H */

Notes:

Shared memory is used for X↔Y communication.
ECC memory support enabled for error detection.
VMEbus configuration for simple A32 slave/master access.

3. Example `main.c`
#

#include "vxWorks.h"
#include "taskLib.h"
#include "semLib.h"
#include "stdio.h"
#include "config.h"
#include "sysLib.h"
#include "vxBusLib.h"

/* Shared Memory Flag */
volatile int *sharedFlag = (int *)SHARED_MEM_BASE;

/* Semaphore for CPU synchronization */
SEM_ID cpuSyncSem;

/* Tick counter for timers */
volatile int tickCount = 0;

/* -----------------------------
   X Processor Initialization
   ----------------------------- */
void xProcessorInit() {
    printf("X CPU initializing...\n");

    /* Set shared memory flag to zero */
    *sharedFlag = 0;

    /* Create semaphore for CPU sync */
    cpuSyncSem = semBCreate(SEM_Q_PRIORITY, SEM_FULL);

    /* Start tick ISR */
    sysIntConnect(MPIC_TIMER_VECTOR, tickISR, 0);
    printf("X CPU initialized.\n");
}

/* -----------------------------
   Y Processor Initialization
   ----------------------------- */
void yProcessorInit() {
    printf("Y CPU initializing...\n");

    /* Wait for X CPU to signal ready */
    while (*sharedFlag == 0) {
        taskDelay(1); // wait 1 tick
    }

    printf("Y CPU detected X CPU ready.\n");
}

/* -----------------------------
   Tick ISR
   ----------------------------- */
void tickISR() {
    tickCount++;
}

/* -----------------------------
   ECC Memory Check Task
   ----------------------------- */
void eccCheckTask() {
    for (;;) {
        if (sysEccErrorDetected())
            printf("ECC memory error detected!\n");
        taskDelay(100);
    }
}

/* -----------------------------
   Main Application
   ----------------------------- */
void main(void) {

#if (CPU == X_CPU)
    xProcessorInit();

    /* Signal Y CPU that X is ready */
    *sharedFlag = 1;

    /* Start ECC memory check task */
    taskSpawn("tEccChk", 100, 0, 2000, (FUNCPTR)eccCheckTask,0,0,0,0,0,0,0,0,0,0);

#elif (CPU == Y_CPU)
    yProcessorInit();
#endif

    /* Example VME Access */
    volatile unsigned int *vmeSlave = (unsigned int *)VME_A32_SLV_BUS;
    *vmeSlave = 0xDEADBEEF;
    printf("VME slave wrote: 0x%X\n", *vmeSlave);

    /* Example main loop */
    for (;;) {
        printf("CPU %d Tick: %d\n", CPU, tickCount);
        taskDelay(60); /* 1-second interval at 60 Hz */
    }
}

Key Features:

Dual-processor boot and synchronization using shared memory.
ECC memory check task running on X CPU.
Tick ISR updating tickCount every timer interrupt.
VMEbus slave write example.
Safe taskDelay loops for cooperative scheduling.

4. Multi-Processor Boot Instructions
#

Load boot ROMs:

boot device          : esyf
unit number          : 0
processor number     : 0
file name            : /path/to/vxWorks

Configure secondary CPU:

sm=0x4100   # shared memory base

Ensure config.h maps CPU numbers correctly (X_CPU=0, Y_CPU=1).
Start Tornado IDE, build kernel, load to target board.

5. Practical Tips
#

Debugging: Use WindView or logMsg for inter-CPU communication traces.
Shared Memory Conflicts: Protect writes with semaphores if multiple variables are accessed.
Timers: Keep tick ISR short; heavy computation in tasks.
VMEbus: Always verify address mapping; unsafe writes may crash system.

6. Expansion Ideas
#

Add UART console task on Y CPU.
Integrate WindView multi-processor logging.
Extend VMEbus routines for block read/write.
Implement inter-CPU messaging queues using msgQLib.

This template provides a fully functional dual-processor setup for VxWorks on Synergy Microsystems PowerPC boards, ready for Tornado IDE. Developers can customize tasks, memory access, timers, and VMEbus routines for their projects.

This example is ready to build and includes: