Synergy Microsystems VxWorks BSP Guide: PowerPC Boards Detailed Reference

Synergy Microsystems VxWorks BSP Guide: PowerPC Boards Detailed Reference

This comprehensive guide provides a fully enriched technical reference for Synergy Microsystems PowerPC VMEbus and Compact PCI boards, translating the original BSP manual into a modern, developer-friendly format. It covers installation, configuration, multi-processor architecture, memory, caches, I/O, timers, interrupts, and debugging with practical examples, tables, and enriched code snippets.

📘 Chapter 1: Introduction and Overview

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The BSP serves as the foundation for VxWorks kernel operation on custom hardware. This guide assumes familiarity with embedded systems and PowerPC architecture.

Key Objectives:

• Enable developers to configure config.h and build functional kernels.
• Guide through multi-processor setups with shared memory and interrupts.
• Provide detailed operational examples for VMEbus, PCI, timers, and memory.

Reading Tips:

• Use Adobe Acrobat Reader 4+ with bookmarks for navigation.
• Search within the PDF using Edit → Find.

Typography:

• Courier 11: File paths, commands, and code snippets.
• Techno 11: Hexadecimal values.
• Times 12: Standard text.

Practical Note: Essential during kernel configuration, BSP compilation, and debugging.

🖥️ Chapter 2: Installing VxWorks

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2.1 Installation on IBM PC Host

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1. Insert the BSP CD and run:

setup.exe

2. Choose the installation path:

C:\vxWorks\target\

Post-Installation Cleanup:

• Remove unused board directories.
• Keep dual/quad processor directories: x, y, z, w.
• Never delete target/config/synergy/.

Boot ROM Preparation:

copy bootroms\bootrom.hex target\bootroms\

2.2 Installation on Unix Host

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tar xvf synBSP1_21g.tar -C /target/

Notes:

• Maintain proper permissions: chmod -R 755 /target/
• Remove unnecessary board directories to save space.

🔧 Chapter 3: Revision History & Key Changes

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BSP Version: 1.2 (from revision /01a)

Enhancements:

• Tornado IDE project support for bootable applications.
• Default END Ethernet driver inclusion.
• Dual-CPU memory allocation adjustments.
• Altivec and L2 cache support for G4/7400 processors.
• ECC/Parity memory error detection.
• Updated PCI auto-configuration and WindView support.

Example config.h Pattern:

/* Enable Ethernet driver */
#define INCLUDE_END

/* Enable dual-CPU memory support */
#define INCLUDE_DUAL_CPU_MEM

/* Define boot device */
#define BOOT_DEVICE "esyf"

Tip: Always verify the board’s boot ROM version matches kernel requirements.

📂 Chapter 4: BSP Directories & Boot ROM Compatibility

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Directory Overview:

• synergy/: Common BSP files.
• svgm5*: Single/Dual VGM5 boards.
• svss4x/y/z/w: Quad VSS4 boards.
• kgm5*: CompactPCI boards.

Boot ROM Compatibility:

• Single processor: flexible across versions.
• Dual/Quad: Kernel 1.21c+ requires matching boot ROMs.

Known Issues:

• sm driver hangs on KGM5 with PReP Map A.
• VSS4 ^X restart sequence required.
• Harmless warnings in Y/Z/W compilers.

Practical Fix:

#define SHARED_MEM_MAP CHRP_MAP_B

🔄 Chapter 5: Multi-Processor Board Architecture

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5.1 Core Architecture

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• Each CPU runs its own VxWorks kernel.
• X processor: primary, handles Ethernet, SCSI, interrupts.
• Y/Z/W processors: secondary, rely on shared memory for communication.

5.2 Configuration Example

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#define NUM_TTY 2   /* X uses port 1, Y uses port 2 */

/* Shared memory base for dual/quad */
#define SHARED_MEM_BASE 0x4100
#define SHARED_MEM_SIZE 0x10000

Exception Handling: Use synExcArchLib.o to manage shared vector table at 0x100.

Tip: Use a single Tornado workspace with separate BSP projects per CPU for multi-processor debugging.

⚙️ Chapter 6: Board Reset, Boot Parameters & Shells

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Reset Methods:

• Hardware: Toggle switches on the board.
• Software:

sysReset();  // Performs software reset

6.1 Ethernet Boot (Single Processor)

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boot device          : esyf
unit number          : 0
processor number     : 0
host name            : YourHost
file name            : /path/to/vxWorks
inet on ethernet (e) : 192.168.1.100

6.2 Multi-Processor Boot

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X Processor: esyf
Y/Z/W: sm=0x4100  // shared memory base

Tornado vs Target Shell Config:

#define INCLUDE_CONFIGURATION_5_2

🧠 Chapter 7: Memory – ECC, Page Tables & Allocation

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7.1 ECC/Parity Support

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#define INCLUDE_RAM_PAR_ECC
#define ECC_MULTIBIT_MCP_ENABLE TRUE
#define ECC_1BIT_MCP_ENABLE     TRUE
#define ECC_TRIGGER_VALUE       32

7.2 Page Tables

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• Required for memory >256MB or exhausted DBATs.
• Example for X processor:

SYS_MEM_DESC sysPhysMemDesc[] = {
    {0x00000000, 0x00005000, VM_PAGE_UNCACHED}, /* first 5 pages uncached */
    {0x00005000, 0x1FFFB000, VM_PAGE_CACHED},   /* rest cached */
};

7.3 Memory Scrubber Task

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void memScrubberTask() {
    for (;;) {
        for (int addr = 0; addr < MEM_SIZE; addr += 0x1000)
            *(volatile uint32_t*)addr;
        taskDelay(60);  // Delay in ticks
    }
}

🗄️ Chapter 8: Caches & Memory Restrictions

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L2 Cache: Auto-sized in bootInit.c.

Code Size Limit:

#define INCLUDE_32MB_CODE_LIMIT

For Larger Applications:

• Adjust LOCAL_MEM_SIZE and LOCAL_MEM_AUTOSIZE in config.h.
• Use sysEndOfUsableRam() to dynamically detect available RAM.

🔌 Chapter 9: VME Bus Interfaces

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PCI-VME Bridge (Universe/Alma) vs Direct VME.

Slave Port Example:

#define VME_A32_SLV_BUS  0x20000000
#define VME_A32_SLV_SIZE 0x02000000

Master Ports Configuration:

UNIV_VME_MASTER uMaster[8] = {
    {0xa0000000, 0x30000000, VME_AM_EXT_DATA, 0x10000000, DBAT, VME_STATE_CACHEABLE_NOT},
    {0xa1000000, 0x31000000, VME_AM_EXT_DATA, 0x10000000, DBAT, VME_STATE_CACHEABLE_NOT}
};

Runtime Commands:

sysSlavePortsShow();
sysMasterPortsShow();

🖧 Chapter 10: PCI Bus Interfaces

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Offboard Configuration:

#define PCI_M_SIZE  0x04000000
#define PCI_IO_SIZE 0x00010000

Helper Functions:

• sysBusToLocalAdrsPci()
• sysMasterPortsShowPci()

PEX3 Support:

#define INCLUDE_PEX3

⏱️ Chapter 11: Timers

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Tick Timer: Default 60 Hz using MPIC.

Timer Allocation Table:

Aux | Y Aux | | Quad | X Tick | Y Tick | Z Tick | W Tick |

Timestamp Support:

#define INCLUDE_TIMESTAMP

⚡ Chapter 12: Interrupts & Mailboxes

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VME Interrupts: Routed to X processor by default.

Mailbox Example:

/* Y processor mailbox code in config.h */
#define Y_BLT_MAIL_CODE 0x10

Generate VME Interrupt:

sysBusIntGen(level, vector);

🏗️ Chapter 13: Building Boot ROMs & Kernels

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Using Tornado IDE:

• Open Synergy BSP project.
• Build kernel & boot ROM.
• Load to target board via serial or TFTP.

Manual Build:

cd svgm5x
make clean
make all

Flash File System Support:

#define INCLUDE_FFS_DRV
#define INCLUDE_DOSFS
#define INCLUDE_FLASH_FILE

💾 Chapter 14: NVRAM, SCSI, Flash & Self Test

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Ethernet Address Storage:

#define NV_ENET_ADRS 0xFFE9E778

SCSI Boot Configuration:

#define INCLUDE_SCSI
#define SCSI_HARDDISK_ID 7

Self-Test:

• Call sysSelfTest() after boot.
• Monitor LED patterns for error codes.

🛠️ Chapter 15: Troubleshooting & LED Diagnostics

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Common Recovery: Use ^C after bus errors.

LED Diagnostic Codes:

• 0xA: Boot start
• 0x5: Memory init complete
• 0x4: CPU sync complete
• Consult board manual for full mapping.

Safe VME Probing:

sysVxMemProbe(addr, VX_READ, 4, &value);

Tip: Use with incremental addresses to avoid bus errors on inaccessible VME regions.

⚡ Chapter 16: Advanced Multi-Processor Tips

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• CPU Synchronization: Use semaphores in shared memory.

SEM_ID semX;
semX = semBCreate(SEM_Q_PRIORITY, SEM_FULL);

• Boot Sequence Coordination: Start secondary CPUs after primary initializes shared resources.

• WindView Integration: Use WindView event logging across CPUs for task monitoring.

📊 Chapter 17: Practical Examples

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1. Shared Memory Communication (X → Y):

volatile int *sharedFlag = (int*)SHARED_MEM_BASE;
*sharedFlag = 1;  // X signals Y

2. Timer Interrupt Handler:

void tickISR() {
    tickCount++;
}
sysIntConnect(MPIC_TIMER_VECTOR, tickISR, 0);

3. ECC Memory Check Task:

void eccCheckTask() {
    for (;;) {
        if (sysEccErrorDetected())
            logMsg("ECC error detected\n", 0,0,0,0,0,0);
        taskDelay(100);
    }
}

This enriched guide now combines detailed explanations, practical code snippets, tables, and tips for every aspect of PowerPC VxWorks BSP development, making it a reference for both beginners and advanced developers.

Refer to Synergy PowerPC VxWorks Example Project: Dual-Processor Template for a template providing a fully functional dual-processor setup for VxWorks on Synergy Microsystems PowerPC boards.